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Display Count
Application Schematic and Figure 15 show the ICL8069
VIN
1.2V band-gap voltage source used as the reference for the
-
COUNT = 10, 000 � ----------------(Range = 1)
ICL7129, and the COMMON output as its pre-regulator. The
VREF
(2V Range)
reference voltage for the ICL7129 is set to 1.000V for both
2V and 200mV full-scale operation. VIN � 10
COUNT = 10, 000 � -----------------------(Range = 0)
VREF
(200mV Range)
Multiple Integration A/D Converter
Minimum VREF: 500mV
Equations
Common Mode Input Voltage
Oscillator Frequency
(V- + 1V)
fOSC = 0.45/RC
COSC > 50pF; ROSC > 50k&!
Auto Zero Capacitor: CAZ not used
fOSC (Typ) = 120kHz
Reference Capacitor: 0.1�F
or
fOSC = 120kHz Crystal (Recommended)
VCOM
Oscillator Period
Biased Between V+ and V-.
VCOM E" V+ -2.9V
tOSC = 1/fOSC
Regulation lost when V+ to V-
Integration Clock Period
If VCOM is externally pulled down to (V+ to V-)/2, the
VCOM circuit will turn off.
tCLOCK = 2*tOSC
Power Supply: Single 9V
Integration Period
V+ - V- = 9V
tINT(2V) = 1000*tCLOCK (Range = 1)
Digital supply is generated internally
tINT(200mV) = 10,000*tCLOCK (Range = 0)
VGND E" V+ - 4.5V
60/50Hz Rejection Criterion
Display: Triplexed LCD
tINT/t60Hz or tINT/t50Hz = Integer
Continuity Output On if
Optimum Integration Current
VINHI to VINLO
IINT = 13�A
Conversion Cycle (In Both Ranges)
Full Scale Analog Input Voltage
tCYC = tCLOCK x 30,000
VINFS (Typ) = 200mV or 2V
ZERO-INTEGRATE INT1 DE1
AND LATCH INTEGRATE DE-INTEGRATE REST X10 DE2 REST X10 DE3 ZERO-INTEGRATE
INTEGRATOR
NOTE: Shaded area greatly expanded
RESIDUE
in time and amplitude.
VOLTAGE
1000 CLOCKS 2000
1000 CLOCKS
10,000 CLOCKS CLOCKS
3-40
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